hardware-description-code-verilog-systemverilog-vhdl-amaranth-python-generated-functional
mechanismsingle paperpending review

When hardware description code (Verilog, SystemVerilog, VHDL, Amaranth-Python) is generated from a functional specification that omits security obligations — as real SoC docs do, keeping countermeasures in separate config files — frontier models pass functional tests far more often than security tests, and the model with the highest functional pass rate is not the safest; naming the relevant CWE in the prompt raises the security pass rate sharply, showing the limit is missing awareness of the required obligation rather than inability to write defensive RTL.

Ingested from a paper but not yet reviewed by a human. It is deliberately inert: it does not move any technique’s standing, does not count toward the backtest, and is excluded anywhere a claim would carry weight. Read the source before relying on it.

Capability: Writing secure code and dependencies

Observed on

Five resource-access CWE families that are observable at module ports under black-box simulation; 392 task instances from real open-source SoC IP; five frontier models, zero-shot, .

Sources

  • Measured on a purpose-built 392-instance benchmark with separate functional and security testbenches, five runs per case, mean±std reported; vanilla functional pass 73-79% vs security pass 14-35%, security rising to about 59% mean with the aligned CWE entry supplied. Security testbenches are an operational approximation of the obligation set, and the CWE-supplied condition is an upper-bound cue that also lowered functional pass rates, so the two metrics are not independent.
Status: pending-reviewLast checked: 2026-09-09Evidence activity: not checked yet
Contest this claim

Disagreeing is the most useful thing you can do here. Both sides of every contested claim in this catalog were assembled by the same person, which is its weakest point.

Related claims

Notes

Drafted from the paper by a model and filed unreviewed. Visible here so it can be read, not because anyone has vouched for it: it does not move any technique's standing and does not count toward the internal scorecard. Drafted confidence: medium. Falsifier as drafted: On the same obligation-omitted specifications, a model whose functional pass rate is high also passes security tests at a similar rate, or supplying the aligned CWE entry fails to raise security pass rates. Drafted stance toward models-complied-insecure-completions-large-fraction-time-more: supports -- Extends the software finding to hardware code and adds that greater functional capability does not track greater security in the same setting. Proposed technique, not catalogued: Symbolic inference of implicit security obligations from a spec graph plus CWE ontology, then obligation-guided revision of a functional draft.